1. Field of the Invention
The present invention relates to integrated circuit (IC) technology. More specifically, the present invention pertains to user-configurable interconnections for array logic and other circuitry and such interconnections which may be reconfigurable by the user; i.e., which may be programmed more than once.
2. The Prior Art
An integrated circuit uses a network of metal interconnects between the individual semiconductor components which are patterned with standard photolithographic processes during wafer fabrication. Multiple levels of metalized patterns may be used to increase the flexibility of the interconnects. In Very Large Scale Integration, for example, higher density and more complex wiring networks are needed.
It has long been recognized that a user-programmable interconnect technique or manufacturer programmability just prior to shipment would allow lower tooling costs and faster delivery time. One technique to accomplish this uses lasers to make or break pre-patterned metal interconnects between an array of logic cells. This is usually performed on the finished wafer prior to assembly or actually in an open package. Another approach uses an array of uncommitted interconnect metal lines using anti-fuses consisting of an amorphous silicon alloy sandwiched into insulation holes between third and fourth metal layers to provide electrically programmable links. A different anti-fuse approach is disclosed in co-pending application Ser. No. 909,261, filed Sep. 19, 1986, now U.S. Pat. No. 4,758,745, assigned to the same assignee as the present application.
Such interconnect systems may be used in analog or digital integrated circuits fabricated using bipolar, MOS or other semiconductor technologies. The laser approach requires sophisticated programming equipment and is fairly slow, requiring many hours to pattern one device having a complexity of two-three thousand circuit elements. Some of techniques for electrically programmable techniques are not silicon efficient, have inflexible connectivity or have degraded speed performance. In addition, prior art anti-fuse architectures are only one-time programmable; they cannot be reconfigured.
A gate array circuit is an array of uncommitted gates with uncommitted wiring channels. To implement a particular circuit function, the circuit is mapped into the array and the wiring channels and appropriate connections are mask programmed by the IC gate array vendor to implement the necessary wiring connections that form the circuit function. The gate array vendor then fabricates the circuit according to the constructed masks. Gate arrays are therefore mask programmable and not user programmable.
User-programmable logic arrays are widely used in digital system design in implementing many logic functions and replacing transistor-transistor logic (TTL) parts. Logic arrays currently available include PLA (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), EPLDs (Erasable Programmable Logic Devices) and logic cell arrays using RAM (Random Access Memory) cells to define logic cell function and interconnect configuration. Programmable logic circuit arrays have usually been implemented in bipolar technology using fusible links which, when programmed, define the logic function to be implemented. An example of such a link is the polysilicon fuse which is "programmed" when it is blown and prevents current flow in a circuit. Such fusible links often require large current to operate and require extra area on the IC. The RAM-implemented logic cell array offers more flexibility than the above programmable circuits due to the nature of the array, its logic blocks, and the interconnect capability. However, it has several disadvantages. First, the RAM-implemented interconnect method uses MOS transistors that are costly in area and slow down the performance. Additionally, RAM cell transistors are volatile and will deprogram when power is disconnected. Furthermore, the use of RAM cells to define the logic block function, its architecture and interconnect scheme is very inefficient in area utilization. Finally, configuration information must be loaded from other non-volatile memory devices.
More recently, electrically programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM) technology has been used to construct programmable logic circuit arrays. In the latter case, EPROM or EEPROM cells are programmed and the stored values used to define circuit configuration. Example of prior art programmable logic circuits which utilize EPROM or EEPROM cells include U.S. Pat. No. 4,207,556 to Spilling et al., U.S. Pat. No. 4,433,331 to Kollaritsch, U.S. Pat. No. 4,609,986 to Harthiann et al., U.S. Pat. No. 4,617,479 to Hartmann et al., U.S. Pat. No. 4,761,768 to Turner, et al., and U.S. Pat. No. 4,642,487 to Carter.
The scheme disclosed in U.S. Pat. No. 4,207,556 refers to the use of EPROM transistors to make interconnections in a standard AND/OR array but does not disclose or suggest any way to program these devices when they are incorporated into an array.
U.S. Pat. No. 4,433,331 discloses a PLA having an interconnection matrix which may utilize an electrically programmable memory cell as the interconnect mechanism. A variation of the well-known row/column PLA interconnect matrix is taught. The reference discloses use of the standard memory cell consisting of both a memory transistor and a select device are necessary to program each cross-point of the matrix.
U.S. Pat. No. 4,609,986 discloses another variation of the AND/OR plane used in PLA devices, where interconnections may be made using EPROM devices.
U.S. Pat. No. 4,617,479 discloses the use of floating gate transistors in logic blocks. The transistor may be turned off thus disabling the logic block.
U.S. Pat. No. 4,761,768 discloses a programmable logic device which utilizes floating gate EEPROM cells.
U.S. Pat. No. 4,642,487 discloses a scheme wherein transistors make desired connections depending on the state of serial shift registers which control their gates. The shift registers function as the memory elements.
Existing programmable array logic circuits use an AND plane of gates followed by an OR plane of gates to implement a particular logic function. The AND plane is usually user programmable while the OR plane programming is usually fixed. Variations to this architecture include registered outputs of the OR plane, partitioning of the array into smaller AND--OR arrays or macrocells and programmable input/output (I/0) architecture to implement several options of I/0 requirements. The RAM implemented logic cell array consists of a matrix of configurable blocks which are programmed to implement a particular logic function by loading an internal RAM with the appropriate data pattern. The array has a network of user-programmable MOS transistors acting as electrical switches as well as vertical and horizontal lines or wires to connect the logic blocks together and to the I/0 blocks.
Existing user-programmable array logic circuits described above are useful in implementing certain logic functions but have several disadvantages. First, the use of an AND plane/OR plane combination of gates to implement logic functions is inflexible and is not well suited to the requirements of random logic functions. Second, the utilization factor of such an array is quite low and a large number of gates are wasted. Third, the IC chip area-per-functional capability is usually quite high.
Gate arrays, on the other hand, are more flexible than programmable array logic and much more efficient in their gate utilization and IC chip area utilization. However, their main disadvantage is that they are mask programmable and not user programmable. This results in much higher costs to develop the circuit and its unique mask patterns, and a long turn-around time to order and receive IC chips.